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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver 1. General Description
The DM9161 is a physical layer, single-chip, and low power transceiver for 100BASE-TX and 10BASE-T operations. On the media side, it provides a direct interface either to Unshielded Twisted Pair Category 5 Cable (UTP5) for 100BASE-TX Fast Ethernet, or UTP5/UTP3 Cable for 10BASE-T Ethernet. Through the Media Independent Interface (MII), the DM9161 connects to the Medium Access Control (MAC) layer, ensuring a high inter operability from different vendors. The DM9161 uses a low power and high performance CMOS process. It contains the entire physical layer functions of 100BASE-TX as defined by IEEE802.3u, including the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), 10BASE-TX Encoder/Decoder (ENC/DEC), and Twisted Pair Media Access Unit (TPMAU). The DM9161 provides a strong support for the autonegotiation function, utilizing automatic media speed and protocol selection. Furthermore, due to the built-in wave shaping filter, the DM9161 needs no external filter to transport signals to the media in 100BASE-TX or 10BASE-T Ethernet operation.
2. Block Diagram
100Base-TX 100Base-TX Transceiver PCS
MII Interface
10Base-T TX/RX Module LED Driver Auto-Negotiation
Clock Circuit Block
Biasing/ Power Block
MII Register
MII Management Control
Final Version: DM9161-DS-F02 May 10,2002
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Table of Contents
1. General Description ..............................................3 2. Block Diagram ......................................................3 3. Features................................................................4 4. Pin Configuration: DM9161 LQFP ........................5 5. Pin Description......................................................6 5.1 Normal MII Interface, 21 pins..............................6 5.2 Media Interface, 4 pins........................................8 5.3 LED Interface, 3 pins ..........................................8 5.4 Mode, 2 pins .......................................................8 5.5 Bias and Clock, 4 pins ........................................9 5.6 Power, 13 pins ....................................................9 5.7 Table A................................................................9 5.8 Pin Maps of Normal MII, Reduced MII, and 10Base-T GPSI (7-Wired) Mode ..................... 10 6. LED Configuration...............................................11 7. Functional Description ........................................12 7.1 MII interface ......................................................12 7.2 100Base-TX Operation .....................................14 7.2.1 100Base-TX Transmit....................................14 7.2.1.1 4B5B Encoder.............................................15 7.2.1.2 Scrambler .................................................. .15 7.2.1.3 Parallel to Serial Converter .........................15 7.2.1.4 NRZ to NRZI Encoder.................................15 7.2.1.5 MLT-3 Converter.........................................15 7.2.1.6 MLT-3 Driver ...............................................15 7.2.1.7 4B5B Code Group.......................................16 7.2.2 100Base-TX Receiver....................................17 7.2.2.1 Signal Detect...............................................17 7.2.2.2 Adaptive Equalizer ......................................17 7.2.2.3 MLT-3 to NRZI Decoder .............................17 7.2.2.4 Clock Recovery Module ..............................18 7.2.2.5 NRZI to NRZ ...............................................18 7.2.2.6 Serial to Parallel..........................................18 7.2.2.7 Descrambler ...............................................18 7.2.2.8 Code Group Alignment ...............................18 7.2.2.9 4B5B Decoder.............................................18 7.2.3 10Base-T Operation ......................................18 7.2.4 Collision Detection .........................................18 7.2.5 Carrier Sense.................................................18 7.2.6 Auto-Negotiation ............................................18 7.2.7 MII Serial Management..................................19 7.2.8 Serial Management Interface.........................19 7.2.9 Management Interface - Read Frame
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Structure .........................................................19 7.2.10 Management Interface - Write Frame Structure........................................................19 7.2.11 Power Reduced Mode .................................20 7.2.12 Power Down Mode.......................................20 7.2.13 Reduced Transmit Power Mode ..................20 8. MII Register Description......................................21 8.1 Basic Mode Control Register (BMCR) - 00.......22 8.2 Basic Mode Status Register (BMSR) - 01 ........23 8.3 PHY ID Identifier Register #1 (PHYIDR1) - 02..24 8.4 PHY ID Identifier Register #2 (PHYIDR2) - 03..24 8.5 Auto-negotiation Advertisement Register (ANAR) - 04 ...................................................................25 8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) - 05 .................................................26 8.7 Auto-negotiation Expansion Register (ANER) - 06 ...................................................................27 8.8 DAVICOM Specified Configuration Register (DSCR) -16.......................................................27 8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17.....................................29 8.10 10Base-T Configuration / Status (10BTCSR) - 18 .........................................................................30 8.11 DAVICOM Specified Interrupt Register - 21 ...30 8.12 DAVICOM Specified Receive Error Counter Register (RECR) - 22 .......................................31 8.13 DAVICOM Specified Disconnect Counter Register (DISCR) - 23 ......................................31 8.14 DAVICOM Hardware Reset Latch State Register (RLSR) - 24 .......................................31 9. DC and AC Electrical Characteristics 9.1 Absolute Maximum Ratings( 25C )...................32 9.2 Operating Conditions ........................................32 9.3 DC Electrical Characteristics ............................33 9.4 AC Electrical Characteristics & Timing Waveform .......................................................... 33 9.4.1 TP Interface ...................................................33 9.4.2 Oscillator/Crystal Timing ................................33 9.4.3 MDC/MDIO Timing ........................................34 9.4.4 MDIO Timing when OUTPUT by STA ...........34 9.4.5 MDIO Timing when OUTPUT by DM9161.....34 9.4.6 100Base-TX Transmit Timing Parameters ....35 9.4.7 100Base-TX Transmit Timing Diagram .........35 9.4.8 100Base-TX Receive Timing Parameters .....35 9.4.9 MII 100Base-TX Receive Timing Diagram ....36
Final Version: DM9161-DS-F02 May 10,2002
DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
9.4.10 MII 10Base-T Nibble Transmit Timing Parameters ..................................................36 9.4.11 MII 10Base-T Nibble Transmit Timing Diagram........................................................36 9.4.12 MII 10Base-T Receive Nibble Timing Parameters .................................................. 37 9.4.13 MII 10Base-T Receive Nibble Timing Diagram........................................................37 9.4.14 Auto-negotiation and Fast Link Pulse Timing Parameters ..................................................37 9.4.15 Auto-negotiation and Fast Link Pulse Timing Diagram .......................................................38 9.4.16 RMII Receive Timing Diagram .....................38 9.4.17 RMII Transmit Timing Diagram ....................38 9.4.18 RMII Timing Diagram ...................................39 9.4.19 RMII Timing Parameter................................39 10. Application Notes ..............................................40 10.1 Network Interface Signal Routing....................40 10.2 10Base-T/100Base-TX Application.................40 10.3 10Base-T (Power Reduction Application) .......41 10.4 Power Decoupling Capacitors.........................42 10.5 Ground Plane Layout ......................................43 10.6 Power Plane Partitioning .................................44 10.7 Magnetics Selection Guide .............................45 10.8 Crystal Selection Guide...................................45 11. Package Information .........................................46 12.Order Information...............................................47
Final Version: DM9161-DS-F02 May 10,2002
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver 3. Features
Fully complies with IEEE 802.3u 10Base-T/100BaseTX Comply with ANSI X3T12 TP-PMD 1995 standard Support Auto-Negotiation function, compliant with IEEE 802.3u Fully integrated Physical layer single chip with direct interface to magnetic Integrated 10Base-T and 100Base-TX transceiver On-chip filtering, no need for external filters Selectable repeater or node mode Selectable MII or RMII (Reduced MII) interface. Selectable GPSI (7-Wired) or MII mode at the 10BaseT. Selectable full-duplex or half-duplex operation MII management interface with maskable interrupt output capability Provide Loopback mode for easy system diagnostics LED status outputs indicate Link/ Activity, Speed10/100 and Full-duplex/Collision. Single low power Supply of 3.3V with 0.35m CMOS technology Very Low Power consumption modes: Power Reduced mode (cable detection) Power Down mode Selectable TX drivers for 1:1 or 1.25:1 transformers for additional power reduction. Compatible with 3.3V and 5.0V tolerant I/Os 48-pin LQFP small package (1x1 cm)
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Final Version: DM9161-DS-F02 May 10,2002
DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver 4. Pin Configuration: DM9161 LQFP
RXCLK/SCRAMEN/10BTSER
RXD[0]/PHYAD[0]
RXD[1]/PHYAD[1]
RXD[2]/PHYAD[2] 27
RXD[3]/PHYAD[3] 26
CRS/PHYAD[4]
MDINTR#
COL/RMII
DGND
DVDD
RXEN
36
35
34
33
32
31
30
29
28
RXDV/TESTMODE RXER/RXD[4]/RPTR DVDD RESET# DVDD XT2 XT1 DGND NC AGND BGRESG BGRES
37 38 39 40 41 42 43 44 45 46 47 48 10 11 12 1 2 3 4 5 6 7 8 9
25 24 23 22 21 20
MDIO
MDC DVDD TXCLK/ISOLATE TXEN TXD[0] TXD[1] TXD[2] TXD[3] TXER/TXD[4] DGND CABLESTS/LINKSTS LINK/ACTLED#/OP2
DM9161
19 18 17 16 15 14 13
AGND
AGND
AVDD
AVDD
AVDD
RX+
TX+
RX-
TX-
Final Version: DM9161-DS-F02 May 10,2002
FDX/COLLED#/OP0
SPEEDLED#/OP1
PWRDWN
5
DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver 5. Pin Description
I: Input, O: Output, LI: Latch input when power-up/reset, Z: Tri-State output, U: Pulled up D: Pulled down 5.1 Normal MII Interface, 21 pins Pin No. Pin Name I/O Description 16 TXER/TXD [4] I Transmit Error/The Fifth TXD Data Bit In 100Mbps mode, when the signal indicates active high and TXEN is active, the HALT symbol substitutes the actual data nibble. In 10Mbps, the input is ignored In bypass mode (bypass BP4B5B), TXER becomes the TXD [4] pin, the fifth TXD data bit of the 5B symbol 20,19,18,17 TXD [0:3] I Transmit Data 4-bit nibble data inputs (synchronous to the TXCLK) when in 10/100Mbps nibble mode. In 10Mbps GPSI (7-Wired) mode, the TXD [0] pin is used as the serial data input pin, and TXD [1:3] are ignored. 21 TXEN I Transmit Enable Active high indicates the presence of valid nibble data on the TXD [0:3] for both 100Mbps and 10Mbps nibble modes. In 10Mbps GPSI (7-Wired) mode, active high indicates the presence of valid 10Mbps data on TXD [0]. Transmit Clock The transmitting clock provides the timing reference for the transfer of the TXEN, TXD, and TXER. TXCLK is provided by the PHY 25MHz in 100Mbps nibble mode, 2.5MHz in 10Mbps nibble mode, 10MHz in 10Mbps GPSI (7-Wired) mode ISOLATE Setting: 0: Reg 0.10 will be initialized to "0". 1: Reg 0.10 will be initialized to "1". Management Data Clock Synchronous clock for the MDIO management data. This clock is provided by management entity, and it is up to 2.5MHz Management Data I/O Bi-directional management data which may be provided by the station management entity or the PHY Receive Data Output 4-bit nibble data outputs (synchronous to RXCLK) when in 10/100Mbps MII mode In 10Mbps GPSI (7-Wired) mode, the RXD [0] pin is used as the serial data output pin, and the RXD [1:3] are ignored PHY address [0:3] (power up reset latch input) PHY address sensing input pins Status Interrupt Output: Asserted low whenever there is a status change (link, speed, duplex) The MDINTR# pin has a high impedance output, a 2.2K pulled high resistor is needed
22
TXCLK/ ISOLATE
O, Z, LI (D)
24 25 29,28,27,26
MDC MDIO RXD[0:3] /PHYAD[0:3]
I I/O O, Z, LI (D)
32
MDINTR#
O, Z
6
Final Version: DM9161-DS-F02 May 10,2002
DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
34 RXCLK /SCRAMEN /10BTSER O, Z, LI (U) Receive Clock The received clock provides the timing reference for the transfer of the RXDV, RXD, and RXER. RXCLK is provided by PHY. The PHY may recover the RXCLK reference from the received data or it may derive the RXCLK reference from a nominal clock 25MHz in 100Mbps MII mode, 2.5MHz in 10Mbps MII mode, 10MHz in 10Mbps GPSI (7-Wired) mode SCRAMEN 10BTSER only support for forced 100M mode or 10M mode; not support for auto-negotiation mode (power up reset latch input) 0 = Bypass scramble in 100M mode, GPSI (7-Wired) mode in 10M mode 1 = Enable scramble (default) in 100M mode, MII mode in 10M mode Carrier Sense Detect/ PHYAD[4] Asserted high to indicate the presence of carrier due to receive or transmit activities in half-duplex mode of 10BASE-T or 100BASE-TX. In repeater mode or full-duplex mode, this signal is asserted high to indicate the presence of carrier due to receive activity only This pin is also used as PHYAD [4] (power up reset latch input) PHY address sensing input pin Collision Detection Asserted high to indicate the detection of the collision conditions in halfduplex mode of 10Mbps and 100Mbps. In full-duplex mode, this signal is always logical 0 Reduced MII enable: This pin is also used to select Normal MII or Reduced MII. (power up reset latch input) 0= Normal MII (default) 1= Reduced MII This pin is always pulled low except used as reduced MII Receive Data Valid Asserted high to indicate that the valid data is presented on the RXD [0:3] Test mode control pin (power up reset latch input) 0 = normal operation (default) 1 = enable test mode Receive Data Error/The Fifth RXD Data Bit of the 5B Symbol Asserted high to indicate that an invalid symbol has been detected In decoder bypass mode (bypass BP4B5B), RXER becomes RXD [4], the fifth RXD data bit of the 5B symbol This pin is also used to select Repeater or Node mode. (power up reset latch input) 0 = Node Mode (default) 1 = Repeater Mode Receive Enable Active high enables receive signals RXD [0:3], RXCLK, RXDV and RXCLK. Active low on this input tri-states these output pins. In node application, this pin should be pulled high. In repeater application, this pin may be connected to a repeater controller Reset Active low input that initializes the DM9161.
35
CRS /PHYAD[4]
O, Z, LI (D)
36
COL /RMII
O, Z, LI (D)
37
RXDV /TESTMODE
O, Z, LI (D) O, Z, LI (D)
38
RXER/RXD[4] /RPTR
31
RXEN
I
40
RESET#
I
Final Version: DM9161-DS-F02 May 10,2002
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
5.2 Media Interface, 4 pins Pin No. 3,4 7,8 Pin Name RX+ RXTX+ TXI/O Description I Differential Receive Pair Differential data is received from the media O Differential Transmit Pair/PECL Transmit Pair Differential data is transmitted to the media in TP mode
5.3 LED Interface, 3 pins Pin No. 11 I/O Description O, Full/Half Duplex LED LI Active states indicate the full-duplex mode. Active states see LED (U) configuration Full-Duplex/Collision LED: when bit 5 of register 16 is set high Active states indicate the full-duplex mode or activity Collision LED when in the half-duplex mode. Active states see LED configuration OP0: (power up reset latch input) This pin is used to control the forced or advertised operating mode of the DM9161 according to the Table A. The value is latched into the DM9161 registers at power-up/reset SPEED LED# O, Speed LED /OP1 LI Active states indicate the 100Mbps mode. Active states see LED (U) configuration When bit 6 of Register 16 is set high, it controls the SPEED LED as 100Base-TX SD signal output. For debug only OP1: (power up reset latch input) This pin is used to control the forced or advertised operating mode of the DM9161 according to the Table A. The value is latched into the DM9161 registers at power-up/reset LINK /ACT O, Link LED & Activity LED: LED# LI Active states indicate the good link for 10Mbps and 100Mbps operations. /OP2 (U) It is also an active LED function when transmitting or receiving data. Active states see LED configuration OP2: (power up reset latch input) This pin is used to control the forced or advertised operating mode of the DM9161 according to the Table A. The value is latched into the DM9161 registers at power-up/reset Pin Name FDX /COL LED# /OP0 Pin Name PWRDWN I/O Description I Power Down Control Asserted high to force the DM9161 into power down mode. When in power down mode, most of the DM9161 circuit block's power is turned off, only the MII management interface (MDC, MDIO) logic is available (the PHY should respond to management transactions and should not generate spurious signals on the MII)). To leave power down mode, the DM9161 needs the hardware or software reset with the PWRDWN pin low
12
13
5.4 Mode, 2 pins Pin No. 10
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Final Version: DM9161-DS-F02 May 10,2002
DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
14 CABLESTS /LINKSTS O, Cable Status or Link Status LI This pin is used to indicate the status of the cable connection when power (D) up reset latch low (Default) 0 = Without cable connection 1 = With cable connection This pin is used to indicate the status of the Link connection when power up reset latch high 0 = Without link 1 = With link
5.5 Bias and Clock, 4 pins Pin No. 47 48 42 43 Pin Name BGRESG BGRES XT2 XT1 I/O P O I/O I Description Bandgap Ground Bandgap Voltage Reference Resistor 6.8K ohm Crystal Output; REF_CLK input for RMII mode Crystal Input
5.6 Power, 13 pins Pin No. 1,2 9 5 6 46 23,30,39,41 15,33,44 5.7 Table A
OP2 OP1 OP0 Function
Pin Name AVDD AVDD AGND AGND AGND DVDD DGND
I/O P P P P P P P
Description Analog Receive Power Analog Transmit Power Analog Receive Ground Analog Transmit Ground Analog Substrate Ground Digital Power Digital Ground
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Dual Speed 100/10 HDX Reserved Reserved Manually Select 10TX HDX Manually Select 10TX FDX Manually Select 100TX HDX Manually Select 100TX FDX Auto-negotiation Enables All Capabilities
Final Version: DM9161-DS-F02 May 10,2002
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
5.8 Pin Maps of Normal MII, Reduced MII, and 10Base-T GPSI (7-Wired) Mode Normal MII Mode TXD [0:1] TXD [2:3] TXEN TXER/TXD [4] TXCLK RXD [0:1] RXD[2:3] RXEN RXER/RXD[4]/RPTR/NODE RXDV RXCLK COL CRS (PHYADR [2:4]) (BP4B5B) MDC MDIO RESET# XT1 (25 MHz) MDC MDIO RESET# XT2 (REF_CLK 50MHz) MDC MDIO RESET# XT1 (25 MHz) Reduced MII Mode TXD [0:1] NC TXEN NC NC RXD [0:1] NC DVDD RPTR/NODE CRS DV NC NC NC 10Base-T GPSI (7-Wired) Mode TXD [0] ; TXD [1] = NC NC TXEN NC TXCLK RXD [0] ; RXD [1] = NC NC DVDD RPTR/NODE NC RXCLK COL CRS
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Final Version: DM9161-DS-F02 May 10,2002
DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver 6. LED Configuration
LEDs flash once per 500ms after power-on reset or software reset by writing PHY register. All LED pins are dual function pins, which can be configured as either active high or low by pulling them low or high accordingly. If the pin is pulled high, the LED is active low after reset. Likewise, if the pin is pulled low, the LED is active high.
DM9161
DVDD
300 Ohm
10K Ohm Pull High for Reset
Pull Low for Reset 10K Ohm
300 Ohm
Final Version: DM9161-DS-F02 May 10,2002
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver 7. Functional Description
The DM9161 Fast Ethernet single chip transceiver, providing the functionality as specified in IEEE 802.3u, integrates a complete 100Base-TX module and a complete 10Base-T module. The DM9161 provides a Media Independent Interface (MII) as defined in the IEEE 802.3u standard (Clause 22). The DM9161 performs all PCS (Physical Coding Sublayer), PMA (Physical Media Access), TP-PMD (Twisted Pair Physical Medium Dependent) sublayer, 10Base-T Encoder/Decoder, and Twisted Pair Media Access Unit (TPMAU) functions. Figure 1 shows the major functional blocks implemented in the DM9161.
100Base-TX Transmitter 100Base-TX Receiver 10Base-T Tranceiver Carrier Sense Collision Detection Auto Negotiation
MII Interface
MII Serial Management Interface
Figure 7-1
7.1 MII Interface The DM 9161 provides a Media Independent Interface (MII) as defined in the IEEE 802.3u standard (Clause 22). The purpose of the MII interface is to provide a simple, easy to implement connection between the MAC Reconciliation layer and the PHY. The MII is designed to make the differences between various media transparent to the MAC sublayer. The MII consists of a nibble wide receive data bus, a nibble wide transmit data bus, and control signals to facilitate data transfers between the PHY and the Reconciliation layer. * TXD (transmit data) is a nibble (4 bits) of data that are driven by the reconciliation sublayer synchronously with respect to TXCLK. For each TXCLK period, which TXEN is asserted, TXD (3:0) are accepted for transmission by the PHY. * TXCLK (transmit clock) output to the MAC reconciliation sublayer is a continuous clock that provides the timing reference for the transfer of the TXEN, TXD, and TXER signals. TXEN (transmit enable) input from the MAC reconciliation sublayer indicates that nibbles are being presented on the MII for transmission on the physical medium.
*
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Final Version: DM9161-DS-F02 May 10,2002
DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
MII Interface (continued) * TXER (transmit coding error) transitions are synchronously with respect to TXCLK. If TXER is asserted for one or more clock periods, and TXEN is asserted, the PHY will emit one or more symbols that are not part of the valid data delimiter set somewhere in the frame being transmitted. RXD (receive data) is a nibble (4 bits) of data that are sampled by the reconciliation sublayer synchronously with respect to RXCLK. For each RXCLK period which RXDV is asserted, RXD (3:0) are transferred from the PHY to the MAC reconciliation sublayer. RXCLK (receive clock) output to the MAC reconciliation sublayer is a continuous clock that provides the timing reference for the transfer of the RXDV, RXD, and RXER signals. * RXDV (receive data valid) input from the PHY indicates that the PHY is presenting recovered and decoded nibbles to the MAC reconciliation sublayer. To interpret a receive frame correctly by the reconciliation sublayer, RXDV must encompass the frame, starting no later than the Start-of-Frame delimiter and excluding any End-Stream delimiter. RXER (receive error) transitions are synchronously with respect to RXCLK. RXER will be asserted for 1 or more clock periods to indicate to the reconciliation sublayer that an error was detected somewhere in the frame being transmitted from the PHY to the reconciliation sublayer. CRS (carrier sense) is asserted by the PHY when either the transmit or receive medium is non-idle, and deasserted by the PHY when the transmit and receive medium are idle. Figure 7-2 depicts the behavior of CRS during 10Base-T and 100Base-TX transmission.
*
*
*
*
TXD
IDLE
SSD J/K
Preamble
SFD
Data
ESD T/R
IDLE
CRS
100Base-TX
TXD
Preamble
SFD
Data
EFD
CRS
10Base-T
Figure 7-2
Final Version: DM9161-DS-F02 May 10,2002
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
7.2 100Base-TX Operation The 100Base-TX transmitter receives 4-bit nibble data clocked in at 25MHz at the MII, and outputs a scrambled 5-bit encoded MLT-3 signal to the media at 100Mbps. The on-chip clock circuit converts the 25MHz clock into a 125MHz clock for internal use. The IEEE 802.3u specification defines the Media Independent Interface. The interface specification defines a dedicated receive data bus and a dedicated transmit data bus. These two busses include various controls and signal indications that facilitate data transfers between the DM9161 and the Reconciliation layer. 7.2.1 100Base-TX Transmit The 100Base-TX transmitter consists of the functional blocks shown in figure 7-3. The 100Base-TX transmit section converts 4-bit synchronous data provided by the MII to a scrambled MLT-3 125, a million symbols per second serial data stream.
25M OSCI
LED1-4#
TX CGM
LED Driver
4B/5B Encoder
Scrambler
Parallel to Serial
NRZ to NRZI
NRZI to MLT-3
MLT-3 Driver
100TXD+/-
Rise/Fall Time CTL 25M CLK 125M CLK MII Signals MII Interface/ Control
4B/5B Decoder
Codegroup Alignment
Descrambler
Serial to Parallel
NRZI to NRZ RX CRM
MLT-3 to NRZI
Adaptive EQ
RXI+/-
Digital Logic
10BASE-T Module
RX TX
RXI+/10TXD+/-
Register
Collision Detection
Carrier Sense
AutoNegotiation
Figure 7-3
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Final Version: DM9161-DS-F02 May 10,2002
DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
The block diagram in figure 7-3 provides an overview of the functional blocks contained in the transmit section. The transmitter section contains the following functional blocks: - 4B5B Encoder - Scrambler - Parallel to Serial Converter - NRZ to NRZI Encoder - NRZI to MLT-3 - MLT-3 Driver 7.2.1.1 4B5B Encoder The 4B5B encoder converts 4-bit (4B) nibble data generated by the MAC Reconciliation Layer into a 5-bit (5B) code group for transmission, see reference Table 7-1. This conversion is required for control and packet data to be combined in code groups. The 4B5B encoder substitutes the first 8 bits of the MAC preamble with a J/K code group pair (11000 10001) upon transmit. The 4B5B encoder continues to replace subsequent 4B preamble and data nibbles with corresponding 5B code-groups. At the end of the transmit packet, upon the deassertion of the Transmit Enable signal from the MAC Reconciliation layer, the 4B5B encoder injects the T/R code group pair (01101 00111) indicating end of frame. After the T/R code group pair, the 4B5B encoder continuously injects IDLEs into the transmit data stream until Transmit Enable is asserted and the next transmit packet is detected. The DM9161 includes a Bypass 4B5B conversion option within the 100Base-TX Transmitter for support of applications like 100 Mbps repeaters, which do not require 4B5B conversion. 7.2.1.2 Scrambler The scrambler is required to control the radiated emissions (EMI) by spreading the transmit energy across the frequency spectrum at the media connector and on the twisted pair cable in 100Base-TX operation. By scrambling the data, the total energy presented to the cable is randomly distributed over a wide frequency range. Without the scrambler, energy levels on the cable could peak beyond FCC limitations at frequencies related to repeated 5B sequences like continuous transmission of IDLE symbols. The scrambler output is combined with the NRZ 5B data from the code group encoder via an XOR logic function. The result is a scrambled data stream with sufficient randomization to decrease radiated emissions at critical frequencies. 7.2.1.3 Parallel to Serial Converter The Parallel to Serial Converter receives parallel 5B scrambled data from the scrambler and serializes it (converts it from a parallel to a serial data stream). The serialized data stream is then presented to the NRZ to NRZI encoder block 7.2.1.4 NRZ to NRZI Encoder Since the transmit data stream has been scrambled and serialized, the data must be NRZI encoded for compatibility with the TP-PMD standard for 100Base-TX transmission over Category-5 unshielded twisted pair cable. 7.2.1.5 MLT-3 Converter The MLT-3 conversion is accomplished by converting the data stream output from the NRZI encoder into two binary data streams with alternately phased logic one events. 7.2.1.6 MLT-3 Driver The two binary data streams, created at the MLT-3 converter, are fed to the twisted pair output driver, which converts these streams to current sources and alternately drives either side of the transmit transformer's primary winding, resulting in a minimal current MLT-3 signal. Refer to figure 7-4 for the block diagram of the MLT-3 converter.
Final Version: DM9161-DS-F02 May 10,2002
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
7.2.1.7 4B5B Code Group Symbol 0 1 2 3 4 5 6 7 8 9 A B C D E F I J K T R H V V V V V V V V V V Meaning Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data A Data B Data C Data D Data E Data F Idle SFD (1) SFD (2) ESD (1) ESD (2) Error Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid 4B code 3210 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 undefined 0101 0101 undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined Table 7-1 5B Code 43210 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 00111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001
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Final Version: DM9161-DS-F02 May 10,2002
DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
D
Q Q
CK
.
Binary plus
Binary In
.
Common driver
MLT-3
Binary minus
Binary In
MLT-3
Figure 7-4 7.2.2 100Base-TX Receiver The 100Base-TX receiver contains several function blocks that convert the scrambled 125Mb/s serial data to synchronous 4-bit nibble data, which is then provided to the MII. The receive section contains the following functional blocks: - Signal Detect - Adaptive Equalizer - MLT-3 to NRZI Decoder - Clock Recovery Module - NRZI to NRZ Decoder - Serial to Parallel - Descrambler - Code Group Alignment - 4B5B Decoder 7.2.2.1 Signal Detect The signal detect function meets the specifications mandated by the ANSI XT12 TP-PMD 100Base-TX Standards for both voltage thresholds and timing parameters. 7.2.2.2 Adaptive Equalizer When transmitting data at high speeds over copper twisted pair cable, attenuation based on frequency becomes a concern. In high speed twisted pair signaling, the frequency content of the transmitted signal can vary greatly during normal operation based on the randomness of the scrambled data stream. This variation in signal attenuation caused by frequency variations must be compensated for to ensure the integrity of the received data. In order to ensure quality transmission when employing MLT-3 encoding, the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment. The selection of long cable lengths for a given implementation requires significant compensation, which will be over-kill in a situation that includes shorter, less attenuating cable lengths. Conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. Therefore, the compensation or equalization must be adaptive to ensure proper conditioning of the received signal independent of the cable length. 7.2.2.3 MLT-3 to NRZI Decoder The DM9161 decodes the MLT-3 information from the Digital Adaptive Equalizer into NRZI data. The relation between NRZI and MLT-3 data is shown in figure 7-4.
Final Version: DM9161-DS-F02 May 10,2002
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
7.2.2.4 Clock Recovery Module The Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder. The Clock Recovery Module locks onto the data stream and extracts the 125Mhz reference clock. The extracted and synchronized clock and data are presented to the NRZI to NRZ Decoder. received are the start-of-frame delimiter (J/K symbols). The J/K symbol pair is stripped and two nibbles of preamble pattern are substituted. The last two code groups are the end-of-frame delimiter (T/R symbols). The T/R symbol pair is also stripped from the nibble presented to the Reconciliation layer. 7.2.3 10Base-T Operation 7.2.2.5 NRZI to NRZ The transmit data stream is required to be NRZI encoded in for compatibility with the TP-PMD standard for 100Base-TX transmission over Category-5 unshielded twisted pair cable. This conversion process must be reversed on the receive end. The NRZI to NRZ decoder, receives the NRZI data stream from the Clock Recovery Module and converts it to a NRZ data stream to be presented to the Serial to Parallel conversion block. 7.2.2.6 Serial to Parallel The Serial to Parallel Converter receives a serial data stream from the NRZI to NRZ converter, and converts the data stream to parallel data to be presented to the descrambler. 7.2.2.7 Descrambler Because the scrambling process requires to control the radiated emissions of transmit data streams, the receiver must descramble the receive data streams. The descrambler receives scrambled parallel data streams from the Serial to Parallel converter, descrambles the data streams, and presents the data streams to the Code Group alignment block. 7.2.2.8 Code Group Alignment The Code Group Alignment block receives un-aligned 5B data from the descrambler and converts it into 5B code group data. Code Group Alignment occurs after the J/K is detected, and subsequent data is aligned on a fixed boundary. 7.2.2.9 4B5B Decoder The 4B5B Decoder functions as a look-up table that translates incoming 5B code groups into 4B (Nibble) data. When receiving a frame, the first 2 5-bit code groups The 10Base-T transceiver is IEEE 802.3u compliant. When the DM9161 is operating in 10Base-T mode, the coding scheme is Manchester. Data processed for transmit is presented to the MII interface in nibble format, converted to a serial bit stream, then Manchester encoded. When receiving, the Manchester encoded bit stream is decoded and converted into nibble format for presentation to the MII interface. 7.2.4 Collision Detection For half-duplex operation, a collision is detected when the transmit and receive channels are active simultaneously. When a collision has been detected, it will be reported by the COL signal on the MII interface. Collision detection is disabled in Full Duplex operation. 7.2.5 Carrier Sense Carrier Sense (CRS) is asserted in half-duplex operation during transmission or reception of data. During full-duplex mode, CRS is asserted only during receive operations. 7.2.6 Auto-Negotiation The objective of Auto-negotiation is to provide a means to exchange information between segment linked devices and to automatically configure both devices to take maximum advantage of their abilities. It is important to note that Autonegotiation does not test the link segment characteristics. The Auto-Negotiation function provides a means for a device to advertise supported modes of operation to a remote link partner, acknowledge the receipt and understanding of common modes of operation, and to reject un-shared modes of operation. This allows devices on both ends of a segment to establish a link at the best common mode of operation. If more than one common mode exists between the two devices, a mechanism is provided to allow the devices to resolve to a single mode of operation using a predetermined priority resolution function.
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Auto-Negotiation (continued) Auto-negotiation also provides a parallel detection function for devices that do not support the Autonegotiation feature. During Parallel detection there is no exchange of configuration information, instead, the receive signal is examined. If it is discovered that the signal matches a technology, supported by the receiving device, a connection will be automatically established using that technology. This allows devices, which do not support Auto-negotiation but support a common mode of operation, to establish a link. 7.2.7 MII Serial Management The MII serial management interface consists of a data interface, basic register set, and a serial management interface to the register set. Through this interface it is possible to control and configure multiple PHY devices, get status and error information, and determine the type and capabilities of the attached PHY device(s). The DM9161 management functions correspond to MII specification for IEEE 802.3u-1995 (Clause 22) for registers 0 through 6 with vendor-specific registers 16,17, 18, 21, 22, 23 and 24. In read/write operation, the management data frame is 64-bits long and starts with 32 contiguous logic one bits (preamble) synchronization clock cycles on MDC. The Start of Frame Delimiter (SFD) is indicated by a <01> pattern followed by the operation code (OP):<10> indicates Read operation and <01> indicates Write operation. For read operation, a 2-bit turnaround (TA) filing between Register Address field and Data field is provided for MDIO to avoid contention. Following the turnaround time, 16-bit data is read from or written onto management registers. 7.2.8 Serial Management Interface The serial control interface uses a simple two-wired serial interface to obtain and control the status of the physical layer through the MII interface. The serial control interface consists of MDC (Management Data Clock), and MDI/O (Management Data Input/Output) signals. The MDIO pin is bi-directional and may be shared by up to 32 devices.
7.2.9 Management Interface - Read Frame Structure
MDC MDIO Read 32 "1"s Idle Preamble 0 SFD 1 1 0 A4 A3 PHY Address Write A0 R4 R3 R0 0 D15 D14 // Data Read // D1 D0 Idle
Z
Op Code
Register Address
Turn Around
7.2.10 Management Interface - Write Frame Structure
MDC MDIO Write 32 "1"s Idle Preamble 0 SFD 1 0 1 A4 A3 PHY Address A0 R4 R3 R0 1 0 D15 D14 Data D1 D0 Idle
Op Code
Register Address Write
Turn Around
Figure 7-5
Final Version: DM9161-DS-F02 May 10,2002
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
7.2.11 Power Reduced Mode The Signal detect circuit is always turned on to monitor whether there is any signal on the media. In case of cable disconnection,, DM9161 will automatically turn off the power and enter the Power Reduced mode, regardless of its operation mode being N-way auto-negotiation or forced mode. While in the Power Reduced mode, the transmit circuit will continue sending out fast link pules with minimum power consumption. If a valid signal is detected from the media, which might be N-way fast link pules, 10Base-T normal link pules, or 100Base-TX MLT3 signals, the device wakes up and resumes normal operation mode. Automatic reduced power down mode can be disabled by writing Zero to Reg.16.4. 7.2.12 Power Down Mode Power Down mode is entered by setting Reg.0.11 to ONE or pulling PWRDWN pin high, which disables all transmit and receive functions, and MII interface functions except the MDC/MDIO management interface. 7.2.13 Reduced Transmit Power Mode Additional transmit power reduction can be gained by designing with 1.25:1 turns ration magnetic on its TX side and using a 8.5K resistor on BGRES and BGRESG pins, and the TX+/TX- pulled high resistors being changed from 50 to 78. This configuration could reduce about 20% of transmit power.
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Final Version: DM9161-DS-F02 May 10,2002
DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver 8. MII Register Description
ADD 00 01 Name CONTROL STATUS 14 13 12 11 10 9 8 7 6 Loop Speed Auto-N Power Isolate Restart Full Coll. back select Enable Down Auto-N Duplex Test Reserved Pream. T4 TX FDX TX HDX 10 10 HDX Cap. Supr. Cap. Cap. Cap. FDX Cap. 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 0 Model No. Next FLP Rcv Remote Reserved FC T4 TX FDX TX HDX 10 FDX Page Ack Fault Adv Adv Adv Adv Adv LP Next LP LP Reserved LP LP LP LP LP Page Ack RF FC T4 TX FDX TX HDX 10 FDX Reserved BP 4B5B 100 FDX Rsvd INTR PEND BP BP BP_A Repeat TX Rsvd SCR ALIGN DPOK mode Select 100 10 10 Reserved HDX FDX HDX LP HBE SQUE JAB 10T Enable Enable Enable Enable Serial Rsvd Rsvd Rsvd FDX SPD Link Mask Mask Mask 15 Reset 5 4 3 2 Reserved 1 0
Auto-N Remote Auto-N Link Jabber Compl. Fault Cap. Status Detect 0 10 HDX Adv LP 10 HDX 0 0
Extd Cap.
02 03 04 05 06 16 17 18 21 22 23 24
PHYID1 PHYID2 Auto-Neg. Advertise Link Part. Ability Auto-Neg. Expansion Aux. Config. Aux. Conf/Stat 10T Conf/Stat MDINTR Rcv Error Counter Disconnect Counter Rstlh Stat
0 0 0 Version No. Advertised Protocol Selector Field Link Partner Protocol Selector Field LP Next Next Pg New Pg LP AutoN Pg Able Able Rcv Cap. Reset Pream. Sleep Remote St. Mch Supr. mode LoopOut Auto-N. Monitor Bit [3:0] Polarity Reverse INTR Status
Pardet Fault RMII Force SPDLE COLLE RPDCT Enable 100LNK D_CTL D_CTL R-EN PHY ADDR [4:0] Reserved
INTR Rsvd Rsvd Mask Receive Error Counter
Rsvd
FDX SPD Link Rsvd Change Change Change
Reserved 0 0 LH_ ISO LH_ CSTS LH_ RMII LH_ LH_ LH_ SCRAM REP T5TMOD LH_OP [2:0]
Disconnect Counter LH_PHYAD [4:0}
Key to Default In the register description that follows, the default column takes the form: , / Where : 1 Bit set to logic one 0 Bit set to logic zero X No default value (PIN#) Value latched in from pin # at reset : RO = Read only RW = Read/Write : SC = Self clearing P = Value permanently set LL = Latching low LH = Latching high
Final Version: DM9161-DS-F02 May 10,2002
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
8.1 Basic Mode Control Register (BMCR) - 00 Bit 0.15 Bit Name Reset Default Description 0, RW/SC Reset 1=Software reset 0=Normal operation This bit sets the status and controls the PHY registers to their default states. This bit, which is self-clearing, will keep returning a value of one until the reset process is completed 0, RW Loopback Loop-back control register 1 = Loop-back enabled 0 = Normal operation When in 100Mbps operation mode, setting this bit may cause the descrambler to lose synchronization and produce a 720ms "dead time" before any valid data appears at the MII receive outputs 1, RW Speed Select 1 = 100Mbps 0 = 10Mbps Link speed may be selected either by this bit or by auto-negotiation. When auto-negotiation is enabled and bit 12 is set, this bit will return auto-negotiation selected medium type 1, RW Auto-negotiation Enable 1 = Auto-negotiation is enabled, bit 8 and 13 will be in auto-negotiation status 0, RW Power Down While in the power-down state, the PHY should respond to management transactions. During the transition to power-down state and while in the power-down state, the PHY should not generate spurious signals on the MII 1=Power down 0=Normal operation 0,RW Isolate 1 = Isolates the DM9161 from the MII with the exception of the serial management. (When this bit is asserted, the DM9161 does not respond to the TXD [0:3], TX_EN, and TX_ER inputs, and it shall present a high impedance on its TX_CLK, RX_CLK, RX_DV, RX_ER, RX [0:3], COL and CRS outputs. When PHY is isolated from the MII it shall respond to the management transactions) 0 = Normal operation 0,RW/SC Restart Auto-negotiation 1 = Restart auto-negotiation. Re-initiates the auto-negotiation process. When auto-negotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. This bit is self-clearing and it will keep returning to a value of 1 until autonegotiation is initiated by the DM9161. The operation of the autonegotiation process will not be affected by the management entity that clears this bit 0 = Normal operation
0.14
Loopback
0.13
Speed selection
0.12 0.11
Auto-negotiation enable Power down
0.10
Isolate
0.9
Restart Auto-negotiation
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
0.8 Duplex mode 1,RW Duplex Mode 1 = Full duplex operation. Duplex selection is allowed when Autonegotiation is disabled (bit 12 of this register is cleared). With autonegotiation enabled, this bit reflects the duplex capability selected by auto-negotiation 0 = Normal operation Collision Test 1 = Collision test enabled. When set, this bit will cause the COL signal to be asserted in response to the assertion of TX_EN 0 = Normal operation Reserved Read as 0, ignore on write
0.7
Collision test
0,RW
0.6-0.0
Reserved
0,RO
8.2 Basic Mode Status Register (BMSR) - 01 Bit 1.15 1.14 1.13 1.12 1.11 1.10-1.7 1.6 Bit Name 100BASE-T4 100BASE-TX full-duplex 100BASE-TX half-duplex 10BASE-T full-duplex 10BASE-T half-duplex Reserved MF preamble suppression Auto-negotiation Complete Remote fault Default 0,RO/P 1,RO/P 1,RO/P 1,RO/P 1,RO/P 0,RO 0,RO Description 100BASE-T4 Capable 1 = DM9161 is able to perform in 100BASE-T4 mode 0 = DM9161 is not able to perform in 100BASE-T4 mode 100BASE-TX Full Duplex Capable 1 = DM9161 is able to perform 100BASE-TX in full duplex mode 0 = DM9161 is not able to perform 100BASE-TX in full duplex mode 100BASE-TX Half Duplex Capable 1 = DM9161 is able to perform 100BASE-TX in half duplex mode 0 = DM9161 is not able to perform 100BASE-TX in half duplex mode 10BASE-T Full Duplex Capable 1 = DM9161 is able to perform 10BASE-T in full duplex mode 0 = DM9161 is not able to perform 10BASE-TX in full duplex mode 10BASE-T Half Duplex Capable 1 = DM9161 is able to perform 10BASE-T in half duplex mode 0 = DM9161 is not able to perform 10BASE-T in half duplex mode Reserved Read as 0, ignore on write MII Frame Preamble Suppression 1 = PHY will accept management frames with preamble suppressed 0 = PHY will not accept management frames with preamble suppressed Auto-negotiation Complete 1 = Auto-negotiation process completed 0 = Auto-negotiation process not completed Remote Fault 1 = Remote fault condition detected (cleared on read or by a chip reset). Fault criteria and detection method is DM9161 implementation specific. This bit will set after the RF bit in the ANLPAR (bit 13, register address 05) is set 0 = No remote fault condition detected Auto Configuration Ability 1 = DM9161 is able to perform auto-negotiation 0 = DM9161 is not able to perform auto-negotiation Link Status
23
1.5 1.4
0,RO 0, RO/LH
1.3 1.2
Auto-negotiation ability Link status
1,RO/P 0,RO/LL
Final Version: DM9161-DS-F02 May 10,2002
DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
1 = Valid link is established (for either 10Mbps or 100Mbps operation) 0 = Link is not established The link status bit is implemented with a latching function, so that the occurrence of a link failure condition causes the link status bit to be cleared and remain cleared until it is read via the management interface Jabber Detect 1 = Jabber condition detected 0 = No jabber This bit is implemented with a latching function. Jabber conditions will set this bit unless it is cleared by a read to this register through a management interface or a DM9161 reset. This bit works only in 10Mbps mode Extended Capability 1 = Extended register capable 0 = Basic register capable only
1.1
Jabber detect
0, RO/LH
1.0
Extended capability
1,RO/P
8.3 PHY ID Identifier Register #1 (PHYID1) - 02 The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9161. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E. Bit 2.15-2.0 Bit Name OUI_MSB Default <0181h> Description OUI Most Significant Bits This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of this register respectively. The most significant two bits of the OUI are ignored (the IEEE standard refers to these as bit 1 and 2)
8.4 PHY ID Identifier Register #2 (PHYID2) - 03 Bit 3.15-3.10 3.9-3.4 3.3-3.0 Bit Name OUI_LSB VNDR_MDL MDL_REV Default <101110>, RO/P <001000>, RO/P <0001>, RO/P Description OUI Least Significant Bits Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this register respectively Vendor Model Number Six bits of vendor model number mapped to bit 9 to 4 (most significant bit to bit 9) Model Revision Number Four bits of vendor model revision number mapped to bit 3 to 0 (most significant bit to bit 3)
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
8.5 Auto-negotiation Advertisement Register (ANAR) - 04 This register contains the advertised abilities of this DM9161 device as they will be transmitted to its link partner during Auto-negotiation. Bit 4.15 Bit Name NP Description Next page Indication 0 = No next page available 1 = Next page available The DM9161 has no next page, so this bit is permanently set to 0 0,RO Acknowledge 1 = Link partner ability data reception acknowledged 0 = Not acknowledged The DM9161's auto-negotiation state machine will automatically control this bit in the outgoing FLP bursts and set it at the appropriate time during the auto-negotiation process. Software should not attempt to write to this bit. 0, RW Remote Fault 1 = Local device senses a fault condition 0 = No fault detected X, RW Reserved Write as 0, ignore on read 0, RW Flow Control Support 1 = Controller chip supports flow control ability 0 = Controller chip doesn't support flow control ability 0, RO/P 100BASE-T4 Support 1 = 100BASE-T4 is supported by the local device 0 = 100BASE-T4 is not supported The DM9161 does not support 100BASE-T4 so this bit is permanently set to 0 1, RW 100BASE-TX Full Duplex Support 1 = 100BASE-TX full duplex is supported by the local device 0 = 100BASE-TX full duplex is not supported 1, RW 100BASE-TX Support 1 = 100BASE-TX half duplex is supported by the local device 0 = 100BASE-TX half duplex is not supported 1, RW 10BASE-T Full Duplex Support 1 = 10BASE-T full duplex is supported by the local device 0 = 10BASE-T full duplex is not supported 1, RW 10BASE-T Support 1 = 10BASE-T half duplex is supported by the local device 0 = 10BASE-T half duplex is not supported <00001>, RW Protocol Selection Bits These bits contain the binary encoded protocol selector supported by this node <00001> indicates that this device supports IEEE 802.3 CSMA/CD Default 0,RO/P
4.14
ACK
4.13 4.12-4.11 4.10 4.9
RF Reserved FCS T4
4.8 4.7 4.6 4.5 4.4-4.0
TX_FDX TX_HDX 10_FDX 10_HDX Selector
Final Version: DM9161-DS-F02 May 10,2002
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10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) - 05 This register contains the advertised abilities of the link partner when received during Auto-negotiation. Bit 5.15 5.14 Bit Name NP ACK Description Next Page Indication 0 = Link partner, no next page available 1 = Link partner, next page available 0, RO Acknowledge 1 = Link partner ability data reception acknowledged 0 = Not acknowledged The DM9161's auto-negotiation state machine will automatically control this bit from the incoming FLP bursts. Software should not attempt to write to this bit 0, RO Remote Fault 1 = Remote fault indicated by link partner 0 = No remote fault indicated by link partner 0, RO Reserved Read as 0, ignore on write 0, RO Flow Control Support 1 = Controller chip supports flow control ability by link partner 0 = Controller chip doesn't support flow control ability by link partner 0, RO 100BASE-T4 Support 1 = 100BASE-T4 is supported by the link partner 0 = 100BASE-T4 is not supported by the link partner 0, RO 100BASE-TX Full Duplex Support 1 = 100BASE-TX full duplex is supported by the link partner 0 = 100BASE-TX full duplex is not supported by the link partner 0, RO 100BASE-TX Support 1 = 100BASE-TX half duplex is supported by the link partner 0 = 100BASE-TX half duplex is not supported by the link partner 0, RO 10BASE-T Full Duplex Support 1 = 10BASE-T full duplex is supported by the link partner 0 = 10BASE-T full duplex is not supported by the link partner 0, RO 10BASE-T Support 1 = 10BASE-T half duplex is supported by the link partner 0 = 10BASE-T half duplex is not supported by the link partner <00000>, RO Protocol Selection Bits Link partner's binary encoded protocol selector Default 0, RO
5.13 5.12-5.11 5.10 5.9 5.8 5.7 5.6 5.5 5.4-5.0
RF Reserved FCS T4 TX_FDX TX_HDX 10_FDX 10_HDX Selector
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
8.7 Auto-negotiation Expansion Register (ANER)- 06 6.15-6.5 6.4 6.3 6.2 Reserved PDF LP_NP_ABLE NP_ABLE 0, RO 0, RO/LH 0, RO 0,RO/P Reserved Read as 0, ignore on write Local Device Parallel Detection Fault PDF = 1: A fault detected via parallel detection function. PDF = 0: No fault detected via parallel detection function Link Partner Next Page Able LP_NP_ABLE = 1: Link partner, next page available LP_NP_ABLE = 0: Link partner, no next page Local Device Next Page Able NP_ABLE = 1: DM9161, next page available NP_ABLE = 0: DM9161, no next page DM9161 does not support this function, so this bit is always 0 New Page Received A new link code word page received. This bit will be automatically cleared when the register (register 6) is read by management Link Partner Auto-negotiation Able A "1" in this bit indicates that the link partner supports Autonegotiation
6.1 6.0
PAGE_RX LP_AN_ABLE
0, RO/LH 0, RO
8.8 DAVICOM Specified Configuration Register (DSCR) - 16 Bit 16.15 16.14 16.13 Bit Name BP_4B5B BP_SCR BP_ALIGN Description Bypass 4B5B Encoding and 5B4B Decoding 1 = 4B5B encoder and 5B4B decoder function bypassed 0 = Normal 4B5B and 5B4B operation 0, RW Bypass Scrambler/Descrambler Function 1 = Scrambler and descrambler function bypassed 0 = Normal scrambler and descrambler operation 0, RW Bypass Symbol Alignment Function 1 = Receive functions (descrambler, symbol alignment and symbol decoding functions) bypassed. Transmit functions (symbol encoder and scrambler) bypassed 0 = Normal operation 0, RW BYPASS ADPOK Force signal detector (SD) active. This register is for debug only, not release to customer 1=Forced SD is OK, 0=Normal operation (Pin#38),RW Repeater/Node Mode The value of the Repeater/Node pin (38) is latched into this bit at power-up/reset 1 = Repeater mode 0 = Node mode 1, RW 100BASE-TX Mode Control 1 = 100BASE-TX operation 1, RO Reserved (Pin#36), RW Reduced MII Enable Select normal MII or reduced MII. The value of the RMII pin(36) is
27
Default 0,RW
16.12
BP_ADPOK
16.11
REPEATER
16.10 16.9 16.8
TX Reserved RMII_Enable
Final Version: DM9161-DS-F02 May 10,2002
DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
latched into this bit at power-up/reset 0 = Normal MII 1 = Enable Reduced MII Force Good Link in 100Mbps 0 = Normal 100Mbps operation 1 = Force 100Mbps good link status This bit is useful for diagnostic purposes Speed LED Disable 0 = Normal SPEEDLED output to indicate speed status 1 = Disable SPEEDLED output and enable SD signal monitor (for internal debug). When this bit is set, it controls the SPEEDLED as 100BASE-X SD signal output .For debug only Collision LED Enable 0 = FDX/COLLED output is configured to indicate Full/half duplex status 1 = FDX/COLLED output is configured to indicate Fullduplex/Collision status Reduced Power Down Control Enable This bit is used to enable automatic reduced power down 0 = Disable automatic reduced power down 1 = Enable automatic reduced power down Reset State Machine When writes 1 to this bit, all state machines of PHY will be reset. This bit is self-clear after reset is completed MF Preamble Suppression Control MII frame preamble suppression control bit 1 = MF preamble suppression bit on 0 = MF preamble suppression bit off Sleep Mode Writing a 1 to this bit will cause PHY entering the Sleep mode and power down all circuit except oscillator and clock generator circuit. When waking up from Sleep mode (write this bit to 0), the configuration will go back to the state before sleep; but the state machine will be reset Remote Loopout Control When this bit is set to 1, the received data will loop out to the transmit channel. This is useful for bit error rate testing
16.7
F_LINK_100
0, RW
16.6
SPLED_CTL
0, RW
16.5
COLLED_CTL
0, RW
16.4
RPDCTR-EN
1, RW
16.3
SMRST
0, RW
16.2
MFPSC
0, RW
16.1
SLEEP
0, RW
16.0
RLOUT
0, RW
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17 Bit 17.15 Bit Name 100FDX Default 1, RO Description 100M Full Duplex Operation Mode After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 100M full duplex mode. The software can read bit [15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in the auto-negotiation mode 100M Half Duplex Operation Mode After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 100M half duplex mode. The software can read bit [15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in the auto-negotiation mode 10M Full Duplex Operation Mode After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 10M Full Duplex mode. The software can read bit [15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in the auto-negotiation mode 10M Half Duplex Operation Mode After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it means the operation 1 mode is a 10M half duplex mode. The software can read bit [15:12] to see which mode is selected after auto-negotiation. This bit is invalid when it is not in the auto-negotiation mode Reserved Read as 0, ignore on write PHY Address Bit 4:0 The first PHY address bit transmitted or received is the MSB of the address (bit 4). A station management entity connected to multiple PHY entities must know the appropriate address of each PHY Auto-negotiation Monitor Bits These bits are for debug only. The auto-negotiation status will be written to these bits B3 b2 b1 B0 0000 0001 0010 0011 0100 0101 0110 0111 1000 In IDLE state Ability match Acknowledge match Acknowledge match fail Consistency match Consistency match fail Parallel detects signal_link_ready Parallel detects signal_link_ready fail Auto-negotiation completed successfully
17.14
100HDX
1, RO
17.13
10FDX
1, RO
17.12
10HDX
1, RO
17.1117.9 17.8-17.4
Reserved PHYADR[4:0]
0, RO (PHYADR), RW 0, RO
17.3-17.0
ANMB[3:0]
Final Version: DM9161-DS-F02 May 10,2002
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
8.10 10BASE-T Configuration/Status (10BTCSR) - 18 Bit 18.15 18.14 Bit Name Reserved LP_EN Default 0, RO 1, RW Description Reserved Read as 0, ignore on write Link Pulse Enable 1 = Transmission of link pulses enabled 0 = Link pulses disabled, good link condition forced This bit is valid only in 10Mbps operation Heartbeat Enable 1 = Heartbeat function enabled 0 = Heartbeat function disabled When the DM9161 is configured for full duplex operation, this bit will be ignored (the collision/heartbeat function is invalid in full duplex mode) Squelch Enable 1 = Normal squelch 0 = Low squelch Jabber Enable Enables or disables the Jabber function when the DM9161 is in 10BASE-T full duplex or 10BASE-T transceiver loopback mode 1 = Jabber function enabled 0 = Jabber function disabled 10BASE-T GPSI Mode 1 = 10BASE-T GPSI mode selected 0 = 10BASE-T MII mode selected GPSI mode is not supported for 100Mbps operation Reserved Read as 0, ignore on write Polarity Reversed When this bit is set to 1, it indicates that the 10Mbps cable polarity is reversed. This bit is automatically set and cleared by 10BASE-T module
18.13
HBE
1,RW
18.12 18.11
SQUELCH JABEN
1, RW 1, RW
18.10
10BT_SER
0,RW
18.9-18.1 18.0
Reserved POLR
0, RO 0, RO
8.11 DAVICOM Specified Interrupt Register - 21 Bit 21.15 21.1421.12 21.11 21.10 21.9 Bit Name INTR PEND Reserved FDX mask SPD mask LINK mask Default 0, RO 0, RO 1, RW 1, RW 1, RW Description Interrupt Pending Indicates that the interrupt is pending and is cleared by the current read. This bit shows the same result as bit 0. (INTR Status) Reserved Full-duplex Interrupt Mask When this bit is set, the Duplex status change will not generate the interrupt Speed Interrupt Mask When this bit is set, the Speed status change will not generate the interrupt Link Interrupt Mask
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10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
When this bit is set, the link status change will not generate the interrupt Master Interrupt Mask When this bit is set, no interrupts will be generated under any condition Reserved Duplex Status Change Interrupt "1" indicates a change of duplex since last register read. A read of this register will clear this bit Speed Status Change Interrupt "1" indicates a change of speed since last register read. A read of this register will clear this bit Link Status Change Interrupt "1" indicates a change of link since last register read. A read of this register will clear this bit Reserved Interrupt Status The status of MDINTR#. "1" indicates that the interrupt mask is off that one or more of the change bits are set. A read of this register will clear this bit
21.8 21.7-21.5 21.4 21.3 21.2 21.1 21.0
INTR mask Reserved FDX change SPD change LINK change Reserved INTR status
1, RW 0, RO 0,RO/LH 0, RO/LH 0, RO/LH 0, RO 0, RO/LH
8.12 DAVICOM Specified Receive Error Counter Register (RECR) - 22 Bit 22.15-0 Bit Name Rcv_ Err_ Cnt Default 0, RO Description Receive Error Counter Receive error counter that increments upon detection of REER
8.13 DAVICOM Specified Disconnect Counter Register (DISCR) - 23 Bit 23.1523.8 23.7-23.0 Bit Name Reserved Disconnect Counter Default 0, RO 0, RO Description Reserved Disconnect Counter that increments upon detection of disconnection
8.14 DAVICOM Hardware Reset Latch State Register (RLSR) - 24 Bit 13 12 11 10 9 8 7 6 5 4 Bit Name LH_LEDST LH_CSTS LH_RMII LH_SCRAM LH_REPTR LH_TSTMOD LH_OP2 LH_OP1 LH_OP0 LH_PH4 Default 0 0 0 1 0 0 1 1 1 0 Description TXCLK pin reset latch value CABLESTS pin reset latch value COL pin reset latch value RXCLK pin reset latch value RXDV pin reset latch value RXER pin reset latch value LINKLED pin reset latch value SPOLED pin reset latch value FDXLED pin reset latch value CRS pin reset latch value
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10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
3 2 1 0 LH_PH3 LH_PH2 LH_PH1 LH_PH0 0 0 0 0 RXD3 pin reset latch value RXD2 pin reset latch value RXD1 pin reset latch value RXD0 pin reset latch value
9. DC and AC Electrical Characteristics
9.1 Absolute Maximum Ratings ( 25C ) Symbol DVDD, AVDD VIN VOUT Tstg Tc LT Parameter Supply Voltage DC Input Voltage (VIN) DC Output Voltage(VOUT) Storage Temperature Rang (Tstg) Case Temperature Lead Temp. (TL, Soldering, 10 sec.) Min. -0.3 -0.5 -0.3 -65 0 --Max. 3.6 5.5 3.6 +125 85 235 Unit V V V C C C Conditions
9.2 Operating Conditions Symbol DVDD,AVDD TA Tc PD (Power Dissipation) Parameter Supply Voltage Ambient Temperature Case Temperature 100BASE-TX 10BASE-T TX, normal activity traffic 50% utility. 10BASE-T idle Auto-negotiation Power Reduced Mode (without cable ) Power Down Mode Min. 3.135 ----------------Max. 3.465 70 85 88 70 30 45 18 3 Unit V C C mA mA mA mA mA mA Conditions
As TA = 70C 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated that in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
9.3 DC Electrical Characteristics (DVDD = 3.3V) Symbol Parameter Min. Typ. Max. Unit Conditions TTL Inputs (TXD0~TXD3, TXCLK, MDC, MDIO, TXEN, TXER, RXEN, TESTMODE, RMII, PHYAD0~4, OPMODE0-2, RPTR, BP4B5B, RESET# ) VIL Input Low Voltage ----0.8 V VIH Input High Voltage 2.0 ----V IIL Input Low Leakage Current ----10 uA VIN = 0.4V IIH Input High Leakage Current -----10 uA VIN = 2.7V MII TTL Outputs ( RXD0-RXD3, RXDV, RXER, CRS, COL, MDIO) VOL Output Low Voltage ----0.4 V IOL = 4mA VOH Output High Voltage 2.4 ----V IOH = -4mA Non-MII TTL Outputs (LINKLED#, SPEEDLED#, FDXLED#, MDINTR#) VOL Output Low Voltage ----0.4 V IOL = 2mA VOH Output High Voltage 2.4 ----V IOH = -2mA Receiver VICM RX+/RX- Common mode Input Voltage --1.2 --V 100 Termination Across Transmitter VTD100 100TX+/- Differential Output Voltage 1.9 2.0 2.1 V Peak to Peak ITD100 100TX+/- Differential Output Current 19 20 21 mA
9.4 AC Electrical Characteristics & Timing Waveforms 9.4.1 TP Interface Symbol Parameter tTR/F 100TX+/- Differential Rise/Fall Time tTM 100TX+/- Differential Rise/Fall Time Mismatch tTDC 100TX+/- Differential Output Duty Cycle Distortion tT/T 100TX+/- Differential Output Peak-to-Peak Jitter XOST 100TX+/- Differential Voltage Overshoot 9.4.2 Oscillator/Crystal Timing Symbol tCKC tPWH tPWL Parameter OSC Cycle Time OSC Pulse Width High OSC Pulse Width Low Min. 39.998 16 16 Typ. 40 20 20 Max. 40.002 24 24 Unit ns ns ns Conditions 50ppm
Min. 3.0 0 0 0 0
Typ. -----------
Max. 5.0 0.5 0.5 1.4 5
Unit ns ns ns ns %
Conditions
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
9.4.3 MDC/MDIO Timing Symbol t0
t1 t2 t3
Parameter MDC Cycle Time MDIO Setup Before MDC MDIO Hold After MDC MDC To MDIO Output Delay
Min. 80 10 10 0
Typ. ---------
Max. ------300
Unit ns ns ns ns
Conditions When OUTPUT By STA When OUTPUT By STA When OUTPUT By DM9161
9.4.4 MDIO Timing When OUTPUT by STA
MDC
t0
10ns (Min) t1 MDIO
10ns (Min) t2
9.4.5 MDIO Timing When OUTPUT by DM9161
t0
MDC
0 - 300 ns t3
MDIO
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10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
9.4.6 100BASE-TX Transmit Timing Parameters Symbol tTXc tTXh, tTXl tTXs tTXh tTXOD t1 t2 tTXpd tTXr/f Parameter TXCLK Cycle Time TXCLK High/Low Time TXD [0:3], TXEN, TXER Setup To TXCLK High TXD [0:3], TXEN, TXER Hold From TXCLK High TXCLK to Output Delay TXEN Sampled To CRS Asserted TXEN Sampled To CRS De-asserted TXEN Sampled To TX+/- Out (Tx Latency) 100TX Driver Rise/Fall Time Min. 39.998 16 12 0 ------3 Typ. 40 20 ----4 4 8 4 Max. 40.002 24 ----25 ------5 Unit ns ns ns ns ns BT BT BT ns Conditions 50ppm
90% To 10%, Into 100ohm Differential Note 1. Typical values are at 25and are for design aid only; not guaranteed and not subject to production testing.
9.4.7 100BASE-TX Transmit Timing Diagram
TXCLK tTXS TXD [0:3], TXEN, TXER
tTXc
tTXh
tTXh
tTXOD
t2 t1 tTXpd tTXr/f
CRS 100TX+/-
9.4.8 100BASE-TX Receive Timing Parameters Symbol Parameter Min. Typ. Max. Unit Conditions tRXc RXCLK Cycle Time 39.996 40 40.004 TRXh, tRXl RXCLK High/Low Time 16 20 24 tRXs RXD [0:3], RXDV, RXER Setup To RXCLK High 10 ns tRXh RXD [0:3], RXDV, RXER Hold From RXCLK High 10 ns tRXpd RX+/- In To RXD [0:3] Out (Rx Latency) 15 BT t1 CRS Asserted To RXD [0:3], RXDV, RXER 4 BT t2 CRS De-asserted To RXD [0:3], RXDV, RXER 0 BT t3 RX+/- In To CRS Asserted 10 14 BT t4 RX+/- Quiet To CRS De-asserted 14 18 BT t5 RX+/- In To COL De-Asserted 14 18 BT 1. Typical values are at 25and are for design aid only; not guaranteed and not subject to production testing.
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
9.4.9 MII 100BASE-TX Receive Timing Diagram
RXCLK RXD [0:3], RXDV, RXER
tTXpd
tRXS tRXh
tRXh
tRXc
t1 CRS t3 RX+/t5 t5 COL t4
t2
9.4.10 MII 10BASE-T Nibble Transmit Timing Parameters Symbol tTXs tTXh t1 t2 tTXpd Parameter TXD[0:3), TXEN, TXER Setup To TXCLK High TXD[0:3], TXEN, TXER Hold From TXCLK High TXEN Sampled To CRS Asserted TXEN Sampled To CRS De-asserted TXEN Sampled To 10TXO Out (Tx Latency) Min. 5 5 ------Typ. ----2 15 2 Max. ----4 20 4 Unit ns ns BT BT BT Conditions
9.4.11 MII 10BASE-T Nibble Transmit Timing Diagram
TXCLK tTXS TXD [0:3], TXEN, TXER t1 CRS 10TX+/tTXpd tTXh
t2
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10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
9.4.12 MII 10BASE-T Receive Nibble Timing Parameters Symbol tRXs tRXh tRXpd t1 t2 t3 t4 Parameter RXD [0:3), RXDV, RXER Setup To RXCLK High RXD [0:3], RXDV, RXER Hold From RXCLK High RXI In To RXD [0:3] Out (Rx Latency) CRS Asserted To RXD [0:3], RXDV, RXER CRS De-asserted To RXD [0:3], RXDV, RXER RXI In To CRS Asserted RXI Quiet To CRS De-asserted Min. 5 5 --1 --1 1 Typ. ----7 14 --2 10 Max. ------20 3 4 15 Unit ns ns BT BT BT BT BT Conditions
9.4.13 MII 10BASE-T Receive Nibble Timing Diagram
RXCLK RXD [0:3], RXDV, RXER t1 CRS t3 RX+/t4 t2 tTXpd tRXS tRXh
9.4.14 Auto-negotiation and Fast Link Pulse Timing Parameters Symbol t1 t2 t3 t4 t5 Parameter Clock/Data Pulse Width Clock Pulse To Data Pulse Period Clock Pulse To Clock Pulse Period FLP Burst Width FLP Burst To FLP Burst Period Clock/Data Pulses in a Burst Min. --55.5 111 8 17 Typ. 100 62.5 125 2 Max. --69.5 139 24 33 Unit ns us us ms ms pulse Conditions DATA = 1
9.4.15 Auto-negotiation and Fast Link Pulse Timing Diagram
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10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
Clock Pulse Data Pulse Clock Pulse
FAST LINK PULSES
t1 t2 t3 FLP Burst
t1
FLP Burst
FLP Bursts
t4 t5
9.4.16 RMII Receive Timing Diagram
100 Mb/s Reception with no errors 9.4.17 RMII Transmit Timing Diagram
100 Mb/s Transmission
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10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
9.4.18 RMII Timing Diagram
REF_CLK
Tsu Thold
TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RX_ER
9.4.19 RMII Timing Parameter Symbol Parameter REF_CLK Frequency REF_CLK Duty Cycle TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RX_ER Data Setup to REF_CLK rising edge TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RX_ER Data hold from REF_CLK rising edge Min. 35 4 2 Typ. 50 Max. 65 Unit MHz % ns ns Conditions
Tsu Thold
Final Version: DM9161-DS-F02 May 10,2002
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver 10. Application Notes
10.1 Network Interface Signal Routing Place the transformer as close as possible to the RJ-45 connector. Place all the 50 resistors as close as possible to the DM9161 RX and TX pins. Traces routed from RX and TX to the transformer should run in close pairs directly to the transformer. The designer should be careful not to cross the transmit and receive pairs. As always, vias should be avoided as much as possible. The network interface should be void of any signals other than the TX and RX pairs between the RJ-45 to the transformer and the transformer to the DM9161. There should be no power or ground planes in the area under the network side of the transformer to include the area under the RJ-45 connector (Refer to Figure 4 and 5). Keep chassis ground away from all active signals. The RJ-45 connector and any unused pins should be tied to chassis ground through a resistor divider network and a 2KV bypass capacitor. The Band Gap resistor should be placed as physically close to pin 47 and 48 as possible (refer to Figure 1 and 2 ). The designer should not run any high-speed signal near the Band Gap resistor placement.
10.2 10Base-T/100Base-TX Application
RX+
3 50 1% 4 0.1 F 50 1% AVDD 0.1 F AGND
Transformer
1:1 3 6 1 4 5 1:1
AVDD
RJ45
RX-
DM9161
TX+
78 1% 7 78 1% 8
0.1 F AGND AGND
2 7 8
TX-
0.1 F
BGRESG BGRES
47 48 AGND 6.8K, 1%
75 1%
75 1%
75 1%
75 1%
0.1 F/2KV or 0.01 F/2KV
Chasis GND
Figure 10-1 10.3 10Base-T/100Base-TX (Power Reduction Application)
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10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
RX+
3 50 1% 4 0.1 F 50 1% AVDD 0.1 F AGND
Transformer
1:1 3 6 1 4 5 1.25:1
AVDD
RJ45
RX-
DM9161
TX+
78 1% 7 78 1% 8
0.1 F AGND AGND
2 7 8
TX-
0.1 F
BGRESG BGRES
47 48 AGND 8.5K, 1%
75 1%
75 1%
75 1%
75 1%
0.1 F/2KV or 0.01 F/2KV
Chasis GND
Figure 10-2
Final Version: DM9161-DS-F02 May 10,2002
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
10.4 Power Decoupling Capacitors Davicom Semiconductor recommends that all the decoupling capacitors of all power supply pins are placed as close as possible to the power pads of the DM9161 (The best distance to place is < 3mm from pin). The recommended decoupling capacitance is 0.1F or 0.01F, as required by the design layout.
DVDD
30
39
DVDD DVDD DVDD
23
41
DM9161
AVDD
AVDD
1
2
Figure 10-3
42
9
AVDD
Final Version: DM9161-DS-F02 May 10,2002
DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
10.5 Ground Plane Layout A single ground plane approach is recommended to minimize EMI. Bad ground plane partitioning can cause more EMI emissions that could make the network interface card not compliant with specific FCC regulations (part 15). Figure 10-4 shows a recommended ground layout scheme.
Figure 10-4
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
10.6 Power Plane Partitioning The power planes should be approximately illustrated in Figure 10-5. The ferrite bead used should have an impedance at least 75 at 100MHz. A suitable bead is the Panasonic surface mound bead, part number EXCCL4532U or an equivalent. 10F, 0.1F, and 0.01F electrolytic bypass capacitors should be connected between DVDD and DGND at each side of the ferrite bead.
Analog VDD Plane
Digital VDD Plane
Digital VDD Plane
Figure 10-5
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10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
10.7 Magnetics Selection Guide Refer to Table 10-2 for transformer requirements. Transformers meeting these requirements are available from a variety of magnetic manufacturers. Designers should Manufacturer Pulse Engineering Delta YCL Halo Nano Pulse Inc. Fil-Mag Bel Fuse Valor Macronics test and qualify all magnetics before using them in an application. The transformers listed in Table 10-2 are electrical equivalents, but may not be pin-to-pin equivalents.
Part Number PE-68515, H1078, H1012 , H1102 LF8200, LF8221X 20PMT04, 20PMT05 TG22-3506ND, TD22-3506G1, TG22-S010ND TG22-S012ND NPI 6181-37, NPI 6120-30, NPI 6120-37 NPI 6170-30 PT41715 S558-5999-01 ST6114, ST6118 HS2123, HS2213 Table 10-2
10.8 Crystal Selection Guide A crystal can be used to generate the 25MHz reference clock instead of an oscillator. The crystal must be a fundamental type, series-resonant, connected to XT1 and XT2, and shunt to ground with 22pF capacitors. (See Figure 6.)
Figure 10-6 Crystal Circuit Diagram
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver 11. Package Information
LQFP 48L (F.P. 2mm) Outline Dimensions
unit: inches/mm
y
Symbol A A1 A2 b b1 C C1 D D1 E E1 e L L1 y
Dimensions in inches Min. 0.002 0.053 0.007 0.007 0.004 0.004 Nom. 0.055 0.009 0.008 0.354BSC 0.276BSC 0.354BSC 0.276BSC 0.020BSC 0.018 0.024 0.039REF 0.003MAX 0 3.5 7 0.030 Max. 0.063 0.006 0.057 0.011 0.009 0.008 0.006
Dimensions in mm Min. 0.05 1.35 0.17 0.17 0.09 0.09 Nom. 1.40 0.22 0.20 9.00BSC 7.00BSC 9.00BSC 7.00BSC 0.50BSC 0.45 0.60 1.00REF 0.08MAX 0 3.5 7 0.75 Max. 1.6 0.15 1.45 0.27 0.23 0.20 0.16
Notes: 1. To be determined at seating plane. 2. Dimensions D1 and E 1do not include mold protrusion. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Dimensions b does not include dambar protrusion. Total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. 4. Exact shape of each corner is optional. 5. These dimensions apply to the flat section of the lead between 0.10mm and 0.25mm from the lead tip. 6. A1 is defined as the distance from the seating plane to the lowest point of the package body. 7. Controlling dimension: millimeter. 8. Reference documents: JEDEC MS-026, BBC.
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DM9161
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver 12. Order Information
Part Number DM9161E Disclaimer The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification, and the provisions stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, implied or by description, regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, DAVICOM MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. DAVICOM reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by DAVICOM for such applications. Please note that application circuits illustrated in this document are for reference purposes only. Company Overview DAVICOM Semiconductor, Inc. develops and manufactures integrated circuits for integration into data communication products. Our mission is to design and produce IC products that are the industry's best value for Data, Audio, Video, and Internet/Intranet applications. To achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. Pin Count 48 Package LQFP DAVICOM`s terms and conditions printed on the order acknowledgment govern all sales by DAVICOM. DAVICOM will not be bound by any terms inconsistent with these unless DAVICOM agrees otherwise in writing. Acceptance of the buyer's orders shall be based on these terms.
Products We offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. Our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and Ethernet networking standards.
Contact Windows
For additional information about DAVICOM products, contact the sales department at: Headquarters Hsin-chu Office: 3F, No. 7-2, Industry E. Rd., IX, Science-based Park, Hsin-chu City, Taiwan, R.O.C. TEL: +886-3-5798797 FAX: +886-3-5798858
Sales & Marketing Office: 2F, No. 5, Industrial Rd.IX, Science-based Park, Hsin-chu City, Taiwan, R.O.C. TEL: +886-3-5798797 FAX: +886-3-5646929 Email: sales@davicom.com.tw Web Site: http://www.davicom.com.tw
WARNING
Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function.
Final Version: DM9161-DS-F02 May 10,2002
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